Integrated circuits have become more complicated as circuit density increases each year. As a result, more efficient testing systems and methods that minimize test costs and reduce overhead are becoming increasingly important. These integrated circuit testing systems and methods should guarantee a high fault coverage.
Some integrated circuit testing systems use Automatic Test Equipment (ATE), which inputs test patterns for a test set corresponding to a set of test vectors that are selected to ascertain the correct behavior of a circuit relative to a particular set of faults. A test pattern forms a test vector that is used for testing the circuit together with an expected response.
Some integrated circuits incorporate “Design for Testability” (DFT), which is used to increase the observability or controllability of a circuit design. The integrated circuits often include scan test registers that can be loaded in response to generated cock signals (or pulses). Test points are often introduced as additional circuit inputs and outputs. Any additional logic and test point connections, however, can be reduced by estimating a design's testability and using Automatic Test Pattern Generation (ATPG) software tools to generate tests and fault coverage. For example, different scan-test methods have been designed to partition an integrated circuit and increase observability and control of internal circuit nodes for testing. In this type of design, the “Circuit-Under-Test” (CUT), i.e., integrated circuit to be tested, typically would have two modes of operation, for example, a normal functional mode and a test mode. The change of one mode to the other could be controlled by a mode-select signal and/or by a separate test clock signal, which could be generated by the Automatic Test Pattern Generation software and any associated Automatic Test Equipment.
This type of integrated circuit test technology is based on scan chains. For example, memory elements or other logic circuits are connected into shift registers. In a normal mode, the integrated circuit elements perform regular functions, but in a scan or test mode, the different elements, such as memory elements, become scan cells that are connected together to form a number of shift registers, often called scan chains, which shift in a set of test patterns into the circuit and then shift out of the circuit (or test) the responses to the test patterns. These test responses can be compared to fault-free responses to determine if the Circuit-Under-Test (CUT) works properly.
During a test mode, the scan elements shift data along the scan chain, such as in a shift register. The test pattern is scanned or shifted into the scan filling the scan elements with data. The Circuit-Under-Test returns to its normal functional mode and a system clock causes the test pattern to be stored in the system flip-flops, and applied at primary circuit inputs to be processed by the combinational logic circuitry of the integrated circuit. In a test mode, a resulting pattern stored in a shift register can be shifted out for comparison with the expected response. The Automatic Test Pattern Generation program models the scanned flip-flops and latches to verify any resulting test patterns that are shifted out with an expected response generated from the Automatic Test Pattern Generation program.
As a result, in conventional, scan-based fault testing, some test patterns can be applied to the integrated circuit at a slower speed than the integrated circuit's functional speed. The integrated circuit can be placed in the scan or shift mode and a test pattern is shifted in from the Automatic Test Equipment. The integrated circuit is placed in the capture mode and the response captured. The integrated circuit is placed back in the shift mode and the response shifted out. In some cases, the scanning out of the integrated circuit's response for a test pattern is merged with the scanning in of subsequent test patterns to reduce test application time. This sequence can be coordinated by the external Automatic Test Equipment, which supplies clock signals in the shift and capture mode.
It should be understood that during a shift mode of operation when test patterns are loaded into scan chains in an integrated circuit core, the Automated Test Equipment can supply the clock to the core. During a capture mode, however, when at-speed testing occurs, a phase-locked loop circuit can supply clocks to the core. When switching back and forth between a shift and capture mode, a clock synchronizer can synchronize the clocks between the Automatic Test Equipment and the phase-locked loop to ensure that clock signals to the controller are stable. The input to a clock synchronizer could include phase-locked loop system clocks and a SHIFT_CLK signal from Automatic Test Equipment. Other inputs could be used to switch between the clocks. Different clock synchronization techniques could also be used.
Another type of integrated circuit test is delay fault testing that also uses a scan test to test for high-speed faults. The integrated circuit operates at its rated functional speed. The Automatic Test Equipment can supply clocks of the same frequency as functional or operational speed clocks, but this speed for Automatic Test Equipment can be difficult to achieve with very high speed integrated circuits. Usually, a functional or delayed Automatic Test Pattern Generation program uses a scan in and scan out function, e.g., data is scanned into and out of a scanned chain under test. An input or capture cycle allows any strobe or stabilized data to be transferred through the circuit logic by a system clock pulse at a desired operating speed. After an input cycle, the next scan in/out cycle begins and previous test results could be shifted out while a new test is shifted in.
Some prior art integrated circuit test systems have modified the test vectors coming from the Automatic Test Program Generation software through the use of a programmable clock generator. Such a system is disclosed in U.S. Pat. No. 6,598,192 to McLaurin, et al., the disclosure which is hereby incorporated by reference in its entirety. In that system, an integrated circuit to be tested includes a programmable clock generator, which provides clock signals to different components of the integrated circuit. This clock generator includes a phase-locked loop circuit and one or more choppers that provide a desired waveform to the integrated circuit for testing. The system is used in conjunction with the Automatic Tester Equipment, allowing the integrated circuit to be scan tested at-speed using slower and less expensive testing equipment.
This system is an improvement over other prior art systems in which the Automatic Test Pattern Generator clock data is manipulated to create waveforms that test the launch-to-capture cycle speed. For example, peripheral and core clock signals in a waveform can be created. One clock per interval can install the correct timing relationship for a test to launch the capture cycle at a desired speed. The waveform of the clock signal can be controlled based on the core clock pattern data and one pulse per interval. A second pulse can be used to launch, and a third pulse used to capture a position and simulate the fastest speed.
The Automatic Test Equipment used in these integrated circuit testing systems often is not adequate because of maximum frequency or maximum slew rate limitations associated with integrated circuit testing. As a result, a testing system, such as disclosed in the incorporated by reference '192 patent, requires that the test patterns created by the Automatic Test Pattern Generation software are at a much lower frequency and must be adapted and changed for operational speed testing. Any Test Pattern Generation Process is also dependent on the frequency of the different test clocks required to test the integrated circuit.